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Характеристики
GS-RME5000-V1.0 Gigabit Router Module WIFI Video Transmission MT7621 Chipset Dual-Core MIPS-1004Kc HNAT/HQoS/ Samba/VPN | Обустройство
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| Месяц | Минимальная цена | Макс. стоимость | Цена |
|---|---|---|---|
| Aug-19-2025 | 6389.91 руб. | 6517.82 руб. | 6453 руб. |
| Jul-19-2025 | 5182.75 руб. | 5286.98 руб. | 5234 руб. |
| Jun-19-2025 | 6289.48 руб. | 6415.45 руб. | 6352 руб. |
| May-19-2025 | 6238.5 руб. | 6363.54 руб. | 6300.5 руб. |
| Apr-19-2025 | 4981.61 руб. | 5081.23 руб. | 5031 руб. |
| Mar-19-2025 | 6138.87 руб. | 6261.0 руб. | 6199.5 руб. |
| Feb-19-2025 | 6088.70 руб. | 6210.36 руб. | 6149 руб. |
| Jan-19-2025 | 6037.75 руб. | 6158.3 руб. | 6097.5 руб. |
Описание товара
GS-RME5000
Module
Version 1.0
1. Introdution
General
TheGS-RME5000-V1.0 module use the MT7621A chipset.The MT7621A integrates a dual-core MIPS-1004Kc (880MHz),HNAT/HQoS/ Samba/VPN accelerators,5-port GbE switch, RGMII, USB3.0, USB2.0, 3xPCIe, SD-XC. The powerful CPU with rich portfolio is suitable for 802.11ac, LTE cat4/5, edge, hotspot, VPN,AC (Access Control). It can also connect to touch-panel, ZigBee/Z-Wave for Internet Service Router and Home Security Gateway.
For the next generation router, MT7621A provides several dedicated hardware engines to accelerate the NAT, QoS, Samba and VPN traffic.These accelerators relief the CPU for other upper layer applications.
Features
nEmbedded MIPS1004Kc (880 MHz, Dual-Core)
- 32 KB I-Cache and 32 KB D-Cache per core
- 256 KB L2 Cache (shared by Dual-Core
- SMP capable
- Single processor operation configurable
nGigabit Switch
- 5 ports with full-line rate
- 5-port 10/100/1000Mbps MDI transceivers
n One RGMII/MII interface
n16-bit DDR2/3 up to 256/512 Mbytes
nSPI(2 chip select), NAND Flash(SLC), SDXC,eMMC(4 bits)
nUSB3 x 1+ USB2 x 1 or USB2 x 2 (all host)
nPCIe host x 3
nI2C, UART Lite x 3, JTAG, MDC, MDIO, GPIO
nVoIP support (I2S, PCM)
nAudio interface (SPDIF-Tx, I2S, PCM)
nDeliver the superb Samba performance via USB2.0/USB 3.0/SD-XC
nHW storage accelerator
nHW NAT
- 2Gbps wired speed
- L2 bridge
- IPv4 routing, NAT, NAPT
- IPv6 routing, DS-Lite, 6RD, 6to4
nHW QoS
- 16 hardware queues to guarantee the min/max bandwidth of each flow.
- Seamlessly co-work with HW NAT engine.
- 2Gbps wired speed.
nHW Crypto
Deliver 400~500 Mbps IPSec throughput
nGreen
-Intelligent Clock Scaling (exclusive)
-DDR2/3: ODT off, Self-refresh mode
n Firmware: Linux 2.6 SDK, OpenWRT
nRGMII iNIC Driver: Linux 2.4/2.6
2.Temperature Limit Ratings
Parameter |
Minimum |
Maximum |
Units |
Storage Temperature |
0 |
+40 |
℃ |
Ambient Operating Temperature |
0 |
60 |
℃ |
Junction Temperature |
0 |
125 |
℃ |
3.Functional Block Diagram
4. Electrical Specifications
DC Characteristics
Module |
Voltage |
Design requirements |
GS-RME5000V1.0 |
3.3V |
500mA |
5.Mechanical
Dimensions (mm) |
Length |
Width |
Height |
50 (Tolerance:±0.2mm) |
50 (Tolerance:±0.2mm) |
(Tolerance:±0.2mm) |
The picture of top
The picture of bottom
6.Pins Description
Ports(J12)
Pin |
Function |
Description ion |
1 |
ESW_TXVN_D_P4 |
Gibabit Port4_D- |
2 |
ESW_TXVP_D_P4 |
Gibabit Port4_D+ |
3 |
ESW_TXVN_C_P4 |
Gibabit Port4_C- |
4 |
ESW_TXVP_C_P4 |
Gibabit Port4_C+ |
5 |
ESW_TXVN_B_P4 |
Gibabit Port4_B- |
6 |
ESW_TXVP_B_P4 |
Gibabit Port4_B+ |
7 |
ESW_TXVN_A_P4 |
Gibabit Port4_A- |
8 |
ESW_TXVP_A_P4 |
Gibabit Port4_A+ |
9 |
GND |
Ground |
10 |
ESW_TXVN_D_P3 |
Gibabit Port3_D- |
11 |
ESW_TXVP_D_P3 |
Gibabit Port3_D+ |
12 |
ESW_TXVN_C_P3 |
Gibabit Port3_C- |
13 |
ESW_TXVP_C_P3 |
Gibabit Port3_C+ |
14 |
ESW_TXVN_B_P3 |
Gibabit Port3_B- |
15 |
ESW_TXVP_B_P3 |
Gibabit Port3_B+ |
16 |
ESW_TXVN_A_P3 |
Gibabit Port3_A- |
17 |
ESW_TXVP_A_P3 |
Gibabit Port3_A+ |
18 |
GND |
Ground |
19 |
ESW_TXVN_D_P2 |
Gibabit Port2_D- |
20 |
ESW_TXVP_D_P2 |
Gibabit Port2_D+ |
21 |
ESW_TXVN_C_P2 |
Gibabit Port2_C- |
22 |
ESW_TXVP_C_P2 |
Gibabit Port2_C+ |
23 |
ESW_TXVN_B_P2 |
Gibabit Port2_B- |
24 |
ESW_TXVP_B_P2 |
Gibabit Port2_B+ |
25 |
ESW_TXVN_A_P2 |
Gibabit Port2_A- |
26 |
ESW_TXVP_A_P2 |
Gibabit Port2_A+ |
27 |
GND |
Ground |
28 |
ESW_TXVN_D_P1 |
Gibabit Port1_D- |
29 |
ESW_TXVP_D_P1 |
Gibabit Port1_D+ |
30 |
ESW_TXVN_C_P1 |
Gibabit Port1_C- |
31 |
ESW_TXVP_C_P1 |
Gibabit Port1_C+ |
32 |
ESW_TXVN_B_P1 |
Gibabit Port1_B- |
33 |
ESW_TXVP_B_P1 |
Gibabit Por1_B+ |
34 |
ESW_TXVN_A_P1 |
Gibabit Port1_A- |
35 |
ESW_TXVP_A_P1 |
Gibabit Por1_A+ |
Ports(J15)
Pin |
Function |
Description ion |
36 |
ESW_TXVN_D_P0 |
Port #0 MDI Transceivers |
37 |
ESW_TXVP_D_P0 |
Port #0 MDI Transceivers |
38 |
ESW_TXVN_C_P0 |
Port #0 MDI Transceivers |
39 |
ESW_TXVP_C_P0 |
Port #0 MDI Transceivers |
40 |
ESW_TXVN_B_P0 |
Port #0 MDI Transceivers |
41 |
ESW_TXVP_B_P0 |
Port #0 MDI Transceivers |
42 |
ESW_TXVN_A_P0 |
Port #0 MDI Transceivers |
43 |
ESW_TXVP_A_P0 |
Port #0 MDI Transceivers |
44 |
GND |
Ground |
45 |
USB_DP |
SB Port0 HS/FS/LS data pin Data+ (USB3.0) |
46 |
USB_DM |
USB Port0 HS/FS/LS data pin Data- (USB3.0) |
47 |
GND |
Ground |
48 |
SSUSB_RXP |
USB Port0 SS data pin RX+ (USB3.0) |
49 |
SSUSB_RXN |
USB Port0 SS data pin RX+-(USB3.0) |
50 |
SSUSB_TXN |
USB Port0 SS data pin TX- (USB3.0) |
51 |
SSUSB_TXP |
USB Port0 SS data pin TX+ (USB3.0) |
52 |
GND |
Ground |
53 |
USB_DP_1P |
USB Port1 data pin Data+ (USB2.0) |
54 |
USB_DM_1P |
USB Port1 data pin Data- (USB2.0) |
55 |
RXD3 |
UART RX Data |
56 |
MT6605_INT |
UART RX Data |
57 |
MT6605_IRQ |
UART Clear To Send |
58 |
CTS3_N |
UART Clear To Send |
59 |
RTS2_N |
UART Request To Send |
60 |
TXD3 |
UART TX Data |
61 |
GND |
Ground |
62 |
ND_CLE |
NAND Flash Command Latch Enable |
63 |
ND_WE_N |
NAND Flash Write Enable |
64 |
ND_WP |
NAND Flash Write Protect |
65 |
ND_ALE |
NAND Flash ALE Latch Enable |
66 |
ND_CS_N |
NAND Flash Chip Select |
67 |
ND_RE_N |
NAND Flash Read Enable |
68 |
ND_RB_N |
NAND Flash Ready/Busy |
69 |
ND_D0 |
NAND Flash Data0 |
70 |
ND_D1 |
NAND Flash Data1 |
Ports(J13)
Pin |
Function |
Description ion |
71 |
ND_D2 |
NAND Flash Data2 NAND Flash Data3 NAND Flash Data4 NAND Flash Data5 NAND Flash Data6 NAND Flash Data7 |
72 |
ND_D3 |
NAND Flash Data3 |
73 |
ND_D4 |
NAND Flash Data4 |
74 |
ND_D5 |
NAND Flash Data5 |
75 |
ND_D6 |
NAND Flash Data6 |
76 |
ND_D7 |
NAND Flash Data7 |
77 |
GND |
Ground |
78 |
JTCLK |
JTAG Clock |
79 |
JTRST_N |
JTAG Target Reset |
80 |
JTDI |
JTAG Data Input |
81 |
EJTAG-TDO |
JTAG Data Output |
82 |
DINT |
JTAG NO |
83 |
JTMS |
JTAG Mode Select |
84 |
GND |
Ground |
85 |
WPS |
NC |
86 |
PERST_N |
PCIE |
87 |
PCIE_TX0_P |
PCIE0_TX+ |
88 |
PCIE_TX0_M |
PCIE0_TX- |
89 |
GND |
Ground |
90 |
PCIE_CK0_M |
PCIE0_CLK- |
91 |
PCIE_CK0_P |
PCIE0_CLK+ |
92 |
PCIE_CK1_P |
PCIE1_CLK+ |
93 |
PCIE_CK1_M |
PCIE1_CLK- |
94 |
GND |
Ground |
95 |
PCIE_RXN0 |
PCIE0_RX- |
96 |
PCIE_RXP0 |
PCIE0_RX+ |
97 |
PCIE_RXN1 |
PCIE1_RX- |
98 |
PCIE_RXP1 |
PCIE1_RX+ |
99 |
GND |
Ground |
100 |
PCIE_CK2_P |
PCIE2_CLK+ |
101 |
PCIE_CK2_M |
PCIE2_CLK- |
102 |
PCIE_TX1_M |
PCIE1_TX+ |
103 |
PCIE_TX1_P |
PCIE1_TX- |
104 |
PCIE_RXN2 |
PCIE2_RX- |
105 |
PCIE_RXP2 |
PCIE2_RX+ |
Ports(J14)
Pin |
Function |
Description ion |
106. |
3.3VD |
POWER |
107 |
3.3VD |
POWER |
108 |
3.3VD |
POWER |
109 |
GND |
Ground |
110 |
GND |
Ground |
111 |
GND |
Ground |
112 |
PCIE_TX2_P |
PCIE2_TX+ |
113 |
PCIE_TX2_M |
PCIE2_TX- |
114 |
I2C_SD |
I2C Data |
115 |
I2C_SCLK |
I2C Clock |
116 |
D2DB_PORST_N |
Power on reset |
117 |
UART0_TXD |
UART RX Data |
118 |
UART0_RXD |
UART TX Data |
119 |
GND |
Ground |
120 |
GE_RXCLK |
RGMII2 Rx Clock |
121 |
GE_RXDV |
RGMII2 Rx Data Valid |
122 |
GE_RXD0 |
RGMII2 Rx Data bit #0 |
123 |
GE_RXD1 |
RGMII2 Rx Data bit #1 |
124 |
GE_RXD2 |
RGMII2 Rx Data bit #2 |
125 |
GE_RXD3 |
RGMII2 Rx Data bit #3 |
126 |
GE_TXCLK |
RGMII2 Tx Clock |
127 |
GE_TXEN |
RGMII2 Tx Data Valid |
128 |
GE_MDC |
PHY Management Clock. Note: While RGMII/MII connects to external PHY, this pin is MDC. Else, it should be NC. |
129 |
GE_MDIO |
PHY Management Data. Note: While RGMII/MII connects to external PHY, this pin is MDIO. Else, it should be NC. |
130 |
GND |
Ground |
131 |
GE_TXD0 |
RGMII2 Tx Data bit #0 |
132 |
GE_TXD1 |
RGMII2 Tx Data bit #1 |
133 |
GE_TXD2 |
RGMII2 Tx Data bit #2 |
134 |
GE_TXD3 |
RGMII2 Tx Data bit #0 |
135 |
GND |
Ground |
136 |
ESW_P0_LED_0 |
Port #0 PHY LED indicators |
137 |
ESW_P1_LED_0 |
Port #1PHY LED indicators |
138 |
ESW_P2_LED_0 |
Port #2 PHY LED indicators |
139 |
ESW_P3_LED_0 |
Port #3 PHY LED indicators |
140 |
ESW_P4_LED_0 |
Port #4 PHY LED indicators |
7.Reference schematics
7.1 MT7621-USB/PCIE/SPI/JATG schematics
7.2 MT7621-DDR3/NANDschematics
7.3 MT7621-RGMII-EPHYschematics
7.4 MT7621-POWER schematics
7.5 MT7621-GbE I/Fschematics
7.6 MEM DDR3/NAND FLASHschematics
7.7 POWERschematics
8.Recommended Reflow Profile
Referred to IPC/JEDEC standard.
Peak Temperature : <250°C
Number of Times :≤2 times
ENVIRONMENTAL
Operating
Operating Temperature: 0°C to +60 °C
Relative Humidity: 5-90% (non-condensing)
Storage
Temperature: -10°C to +80°C (non-operating)
Relevant Humidity: 5-95% (non-condensing)
MTBF caculation
Over 150,000hours
9.Precautions before surface mounting:
⑴When customers Open stencil,theymust be sure the holeenoughbigger to the module plate, please press 1to0.7 mm is widened to open outward andthe thickness of 0.12 mm .
⑵whenweneed get the wifi module ,we can'tDirect hand andmustwear the gloves and static ring.
⑶According to the size of the customer ‘sthe mainboard ,the furnace temperaturecan stick on a tablet standard temperature of250 or so up and down no more than 5 degrees and sometimes it even can achieve 260 or so up and down no more than 5 degrees.
⑷Storage and use module control should pay attention to the following matters:
a.The calculated shelf life in a sealed bag is 12 months,stored between 0 °C and 40 °C at less than90% relative humidity (RH).
b.After the bag is opened, devices that are subjected to solder reflow orother high temperature processes must be handled in the following manner:
? Mounted within 168 hours of factory conditions, i.e. < 30°C at 60% RH.
? Storage humidity needs to maintained at < 10% RH.
? Baking is necessary if the customer exposes the component to air for over 168 hrs, baking conditions: 125°C for 8 hours.
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